Principal Design Verification Engineer

Company DescriptionPradhi Semiconductor Private Limited is a stealth-mode, Indian fabless semiconductor company focused on developing a product line and ecosystem for RISC-V SoC products. Role DescriptionThis is a full-time, on-site role for a Principal Design Verification Engineer, based in Hyderabad. Our SoC Engineering division is seeking a skilled design verification engineer to join 5G MPU product development team. As we continue to grow, we need talented engineers responsible for the development of products across Enterprise markets. Qualifications10 years + experience in the role Knowledge of translating chip-level requirements into test plans and test cases. Relate regression results to requirements. Understand details of different types of architecture, industry-standard low power architecture, and build block/chip level testbench using best-in-class verification methodology. Create detailed verification plan from specification and in coordination with architects. Develop reusable block/IP level test bench and support IP integration verification. Generate directed and ingenuous constrained random tests. Create/analyze coverage model and enhance testbench/test to increase coverage. Build automated flows for block and chip level verification. Debug failures, manage bug tracking, and close coverage. Hold detailed verification reviews and set standard for coding quality. Work closely with team members to improve methodology and flow. Make improvements in the development of test benches and simulation performance. Experience in driving high code coverage through assertions and automatic verifiers Perform functional and performance verification. Debug and resolve design and verification issues. Collaborate with design and architecture teams to ensure verification coverage.

Your Profile You are best equipped for this task if you have: General knowledge of the ASIC design process, digital and mixed-signal design. Design verification experience (developing test plan, test bench, testcases, assertions, functional & code coverage, debugging tests and designs). Familiarity with design, verification and assertion languages. SystemVerilog expertise strongly desired. Proficiency in SystemVerilog and UVM (Universal Verification Methodology). Experience with System Verilog Assertion (SVA). Experience with formal verification tool (JasperGold or others) Experience with IP verification method and integration verification. Knowledge with IPs developments and release flow. Programing experience in C, C++ and/or assembly Scripting and automation skills: Unix/Linux shell programming, Python, Perl, etc. Drive functional coverage and RTL code coverage. Experience defining coverage space and writing coverage model. Perform formal verification at the chip level. Experience with industry standard tools and methodologies Experience with embedded processors/firmware development is a plus Experience in the power management industry desired. Experience with low power verification. If interested, please email your resume to