Design Engineering Architect ( Analog Design)
Cadence System Design and Analysis
Job Description
Job DescriptionThe Lead Analog Design Engineer will take a Key role on the Analog and Mixed signal design team as part of a Die to Die Product Development Team.Job Responsibilities:Design of High Speed D2D and SERDES products at industry standard data rates up on leading edge technology nodes (e.g. 3nm FinFET CMOS)Design and development of analog/mixed signal IC circuit blocks from initial concept/specification through final verification of conformance to customer specificationsWork closely with Layout Design Engineers to design IC circuit blocks and PMA sectionsWork with Technical Team Leads in the areas of circuit design and SERDES architecturesWork with global teams (US, west coast and east coast), which work in different time-zones
Job Qualifications:BEng, MEng, PhD or equivalent.Candidate's background should include a minimum of 8 years of CMOS design experience, preferably in the area of CMOS SERDES or high-speed I/O IC designShould have a good understanding of jitter and signal equalization techniquesDesign experience in some of the following SERDES circuit blocks: Driver, Receiver, Serializer, Deserializer, Phase Interpolator, Low jitter PLL, High Speed Clock Distribution, Bias and Bandgap, Voltage RegulatorsExcellent problem-solving skills, analog aptitude, good communication skills and ability to work cooperatively in a team environmentPosition requires proficiency in using CAD tools for circuit simulation, layout and physical verificatio
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Additional Skills/Preferences:Cadence tool experience is desirable and design experience at >10Gbps and in esLab test experience as part of silicon evaluation is advantageo
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