IO/Analog Block Layout Engineer

Job Title: Analog/ IO Block Layout EngineerLocation: Bangalore, India

Job SummaryWe are seeking a highly skilled IO Layout Engineer with strong experience in advanced process nodes to join our VLSI design team. The ideal candidate will have hands-on expertise in IO and analog block layout, working closely with circuit design, packaging, and foundry teams to deliver high-quality silicon across cutting-edge technologies.

Key ResponsibilitiesDesign and develop IO and Analog block layouts, including GPIO and DDR interfaces, for advanced technology nodesPerform full-chip and block-level IO layout, ensuring compliance with foundry and design rulesWork on advanced process technologies including TSMC 2nm, 3nm, 5nm and Samsung Foundry 2nm, 4nm (SF)Collaborate with circuit designers to optimize layout for performance, power, reliability, and manufacturabilityExecute and resolve DRC, LVS, ERC, EM/IR, and reliability checksReview layout against ESD, latch-up, and IO ring requirementsInterface with foundries to resolve process-related layout issues and implement best practicesContribute to layout methodology improvements and automation where applicable

Required Skills & QualificationsStrong experience in IO and Analog Layout, including GPIO and DDRProven hands-on experience with advanced nodes: TSMC: 2nm, 3nm, 5nmSamsung Foundry: 2nm, 4nmSolid understanding of advanced DRC/LVS rules and complex design constraintsFamiliarity with ESD, latch-up prevention, EM/IR, and reliability requirements for IO designsProficiency with industry-standard EDA tools (Cadence Virtuoso or equivalent)Strong understanding of semiconductor manufacturing processes and layout fundamentals

Experience LevelTypically 4+ years of relevant experience in IO/Analog layout (flexible based on skill depth)