System Verification Engineer

The Microcontroller Sub-System IP team plays a crucial role in enabling embedded processing solutions across various functions and products at . This team deals with security, power management, and other system-on-chip (SoC) functions across multiple business units (IoT, Mobile, Auto, XR, Compute, etc.). If you’re passionate about solving complex problems and want to be part of a diverse, multicultural team, read on!

Responsibilities

• Technological Advancements: Be an integral part of our team’s journey toward technological excellence.
• Verification Methodologies: Deploy industry-leading verification methodologies such as Universal Verification Methodology (UVM) and Formal Verification.
• Testbench and Verification Component Development: Create testbenches and verification components, including Universal Verification Components (UVCs), C models, and reusable vertical/horizontal verification environments.
• Coverage Analysis: Ensure comprehensive coverage and collaborate with design teams to address any coverage gaps.
• Cross-Functional Collaboration: Work closely with design, SoC, and validation teams to solve problems at various levels.
• System solutions Support: Assist in integrating design into higher-level subsystems, including test planning, test vector delivery, and test vector debugging.

Qualifications

• Positive Attitude: Bring a fun-loving attitude and a passion for inclusive problem-solving.
• Education: Bachelor’s degree in Science, Engineering, or a related field.
• Experience: 3+ years of ASIC design verification experience, preferably with UVM-based.
• ISA Verification: Familiarity with ARM or RISC‑V ISA verification.
• Formal Verification Tools: Experience using formal verification tools like Jasper or VC_Formal is a plus.
• Microcontroller/Sub‑System Knowledge: Understanding of processor/microcontroller sub-systems is advantageous.
• AMBA Bus Protocols: Familiarity with AMBA bus protocols is desirable.
• Gate‑Level Simulation and Power Extraction: Experience with gate‑level simulation debug and power extraction tools is beneficial.
• Power‑Aware Verification: Knowledge of power‑aware verification methodologies.
• Coverage-Driven Verification: Proficiency in constrained‑random verification environments and coverage‑driven methodologies.
• System Verilog Assertions: Familiarity with System Verilog assertions.
• Debugging Skills: Ability to debug test failures and report verification results to achieve expected code/functional/line coverage goals.
• RTL Simulation Tools: Extensive usage of RTL simulation tools.
• Scripting Proficiency: Skills in UVM, System Verilog, and Perl/Python shell scripting.
• C/C++ Familiarity: Basic familiarity with C/C++.