ISP RTL Design Engineer

ResponsibilitiesResponsible for implementing ISP Algorithm into HW using Verilog, SystemVerilog and/or SystemC (High Level Synthesis)Verify Logic at ISP level and Digital System levelOptimize Design for less gate count and low power consumptionDrive ISP Design activities in close collaboration with ISP Algorithm Team QualificationsMinimum MSEE, or BSEE, or related/equivalent disciplineExperience / knowledge in RTL, C/C++ programming and verificationStrong debugging and problem-solving skillsGood communication and interpersonal skillsResult oriented and embrace change behavioursC++/SystemC knowledge with High Level Synthesis experience is a plus.Experience / knowledge in CMOS Image Sensor is a plus