(Sr./Staff) ISP RTL Design Engineer

ResponsibilitiesResponsible for implementing ISP Algorithm into HW using Verilog, SystemVerilog and/or SystemC (High Level Synthesis)Define ISP HW Architecture based on product features and performance requirements, also with gate count and power estimationVerify Logic at ISP level and Digital System levelOptimize Design for less gate count and low power consumptionDrive ISP Design activities in close collaboration with ISP Algorithm Team RequirementsMinimum MSEE, or BSEE, or equivalent, plus 3+ years of Digital Design and verification related experienceExperience / knowledge in CMOS Image Sensor and image signal processing (ISP)Experience / knowledge in System C/C++, System Verilog, and Catapult HLS tool.Strong debugging and problem-solving skillsGood communication and interpersonal skillsResult oriented and embrace change behaviours